Machine Learning-Optimized Fault Tolerance for Reconfigurable RISC-V Cores

Shukla & Ray (2022) proposed a reconfigurable quad-core RISC-V with DMR-based fault tolerance, but their switching between modes is static. This research introduces reinforcement learning (RL) to predict optimal modes based on workload characteristics (e.g., error rates, power budgets). Similar to MaRVIn’s DSE for mixed-precision DNNs (Armeniakos et al., 2025), the RL agent would analyze telemetry (e.g., thermal sensors, fault-injection data) to decide when to enable redundancy. For example, during space missions, high-radiation events could trigger DMR mode, while routine tasks use all cores for performance. This approach challenges the trade-off in Shukla & Ray’s work by making reconfiguration adaptive rather than deterministic. It also synthesizes concepts from ASH’s hardware-software co-design (Elsabbagh et al., 2023) to implement the RL agent as a microcode extension.

References:

1. A Low-Overhead Reconfigurable RISC-V Quad-Core Processor Architecture for Fault-Tolerant Applications. Satyam Shukla, K. C. Ray (2022). IEEE Access.
2. Accelerating RTL Simulation with Hardware-Software Co-Design. Fares Elsabbagh, Shabnam Sheikhha, Victor A. Ying, Quan M. Nguyen, J. Emer, Daniel Sanchez (2023). Micro.
3. MaRVIn: A Cross-Layer Mixed-Precision RISC-V Framework for DNN Inference, from ISA Extension to Hardware Acceleration. Giorgos Armeniakos, Alexis Maras, Sotirios Xydis, Dimitrios Soudris (2025). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.