Secure Enclaves via RISC-V Spatial Isolation with Minimal Overhead

While Shukla & Ray (2022) used DMR for fault tolerance, this repurposes their reconfigurable quad-core for security. Two cores form a "secure enclave" with physically isolated caches and register files, while others handle untrusted tasks. Unlike TEEs (Trusted Execution Environments) that rely on hypervisors, this uses spatial isolation—inspired by SENECA’s hierarchical controllers (Tang et al., 2023) for resource partitioning. Data transfers between enclaves use custom RISC-V ISAXs (Oppermann et al., 2024) for encrypted channels. This avoids software-based attacks (e.g., Meltdown) with <5% area overhead (vs. 17.89% in Shukla & Ray’s DMR). Verification could use Weingarten et al.’s formal methods (2024) to prove isolation properties. The novelty lies in leveraging fault-tolerance hardware for security, creating a dual-purpose architecture.

References:

1. Complete and Efficient Verification for a RISC-V Processor Using Formal Verification. Lennart Weingarten, Kamalika Datta, Abhoy Kole, Rolf Drechsler (2024). Design, Automation and Test in Europe.
2. A Low-Overhead Reconfigurable RISC-V Quad-Core Processor Architecture for Fault-Tolerant Applications. Satyam Shukla, K. C. Ray (2022). IEEE Access.
3. Longnail: High-Level Synthesis of Portable Custom Instruction Set Extensions for RISC-V Processors from Descriptions in the Open-Source CoreDSL Language. Julian Oppermann, Brindusa Mihaela Damian-Kosterhon, Florian Meisel, Tammo Mürmann, E. Jentzsch, Andreas Koch (2024). International Conference on Architectural Support for Programming Languages and Operating Systems.
4. SENECA: building a fully digital neuromorphic processor, design trade-offs and challenges. Guangzhi Tang, K. Vadivel, Ying Xu, Refik Bilgic, Kevin Shidqi, Paul Detterer, Stefano Traferro, M. Konijnenburg, M. Sifalakis, G. van Schaik, A. Yousefzadeh (2023). Frontiers in Neuroscience.