Self-Verifying RISC-V Processors with Dynamic Anomaly Detection

Weingarten et al. (2024) achieved polynomial-time formal verification for RISC-V processors but focused on offline verification. This idea extends their work by integrating lightweight verification units into the processor pipeline itself. Inspired by Collie’s holistic anomaly detection in RDMA subsystems (Kong et al., 2023), the processor would continuously monitor internal signals (e.g., pipeline stalls, cache misses) using hardware-accelerated property checking. When deviations from expected behavior occur (e.g., timing anomalies from radiation-induced faults, as in Shukla & Ray’s fault-tolerant designs), the core could trigger self-correction or alert systems. This diverges from static verification by enabling runtime assurance with minimal overhead—potentially using ASH’s parallel simulation architecture (Elsabbagh et al., 2023) for efficient on-chip checking. The innovation lies in merging formal methods with real-time monitoring, creating processors that "self-diagnose" without external tools.

References:

1. Complete and Efficient Verification for a RISC-V Processor Using Formal Verification. Lennart Weingarten, Kamalika Datta, Abhoy Kole, Rolf Drechsler (2024). Design, Automation and Test in Europe.
2. Collie: Finding Performance Anomalies in RDMA Subsystems. Xinhao Kong, Yibo Zhu, Huaping Zhou, Zhuo Jiang, Jianxi Ye, Chuanxiong Guo, Danyang Zhuo (2023). Symposium on Networked Systems Design and Implementation.
3. A Low-Overhead Reconfigurable RISC-V Quad-Core Processor Architecture for Fault-Tolerant Applications. Satyam Shukla, K. C. Ray (2022). IEEE Access.
4. Accelerating RTL Simulation with Hardware-Software Co-Design. Fares Elsabbagh, Shabnam Sheikhha, Victor A. Ying, Quan M. Nguyen, J. Emer, Daniel Sanchez (2023). Micro.