Hardware-Accelerated Learned Indexes for Edge Devices via Stochastic Computing

Inspired by Sun et al.'s (2022) SC-based hardware acceleration for RL, this idea applies SC to learned indexes to address their computational cost trade-offs (Choi et al. 2024). Traditional learned indexes rely on floating-point arithmetic, making them unsuitable for resource-constrained edge devices. We propose encoding index models (e.g., linear regressions) as stochastic bitstreams, allowing predictions via simple bitwise operations. This contrasts with Amato et al.'s (2023) neural network-based indexes, which prioritize accuracy over efficiency. By integrating SC with FPGA implementations (Hu 2023), we can achieve 10× lower power consumption than GPU-accelerated designs. The novelty lies in co-designing the index structure and hardware: e.g., using SC-friendly piecewise-linear models instead of complex neural networks. This could enable learned indexes in IoT sensors, reducing query latency to microseconds while maintaining 95% accuracy.

References:

1. Can Learned Indexes be Built Efficiently? A Deep Dive into Sampling Trade-offs. Minguk Choi, Seehwan Yoo, Jongmoo Choi (2024). Proc. ACM Manag. Data.
2. Neural networks as building blocks for the design of efficient learned indexes. Domenico Amato, Giosuè Lo Bosco, R. Giancarlo (2023). Neural computing & applications (Print).
3. Hardware Acceleration for Postdecision State Reinforcement Learning in IoT Systems. Jianchi Sun, Nikhilesh Sharma, Jacob Chakareski, Nicholas Mastronarde, Yingjie Lao (2022). IEEE Internet of Things Journal.
4. FPGA Hardware Acceleration Research and Implementation of Deep Learning Algorithms. Yuxuan Hu (2023). Frontiers in Computing and Intelligent Systems.