Hybrid von Neumann-In-Memory RISC-V Architecture for Adaptive Workloads

Mallios et al. (2024) demonstrated memristive RISC-V extensions for in-memory computing but treated it as a standalone solution. This idea proposes a heterogeneous RISC-V core where standard ALUs coexist with memristive crossbars (Mallios et al., 2024) as coprocessors. A runtime scheduler—inspired by SENECA’s hierarchical controllers (Tang et al., 2023)—would partition instructions: data-parallel tasks (e.g., DNN layers) route to in-memory units, while control-heavy tasks use the pipeline. This addresses the von Neumann bottleneck without fully abandoning traditional designs. Unlike Wang et al.’s XiangShan (2025), which focuses on out-of-order execution, this leverages architectural diversity. The scheduler could use Collie-like anomaly detection (Kong et al., 2023) to identify workloads where in-memory units outperform pipelines, enabling seamless transitions.

References:

1. Collie: Finding Performance Anomalies in RDMA Subsystems. Xinhao Kong, Yibo Zhu, Huaping Zhou, Zhuo Jiang, Jianxi Ye, Chuanxiong Guo, Danyang Zhuo (2023). Symposium on Networked Systems Design and Implementation.
2. XiangShan: An Open Source Project for High-Performance RISC-V Processors Meeting Industrial-Grade Standards. Kaifan Wang, Jian Chen, Yinan Xu, Zihao Yu, Wei He, Dan Tang, Ninghui Sun, Yungang Bao (2025). IEEE Micro.
3. Memristive Based In-Memory Computing Using Novel RISC-V Architectures. Konstantinos-Alexandros Mallios, I. Tompris, A. Passias, Iosif-Angelos Fyrigos, G. Sirakoulis (2024). 2024 Panhellenic Conference on Electronics & Telecommunications (PACET).
4. SENECA: building a fully digital neuromorphic processor, design trade-offs and challenges. Guangzhi Tang, K. Vadivel, Ying Xu, Refik Bilgic, Kevin Shidqi, Paul Detterer, Stefano Traferro, M. Konijnenburg, M. Sifalakis, G. van Schaik, A. Yousefzadeh (2023). Frontiers in Neuroscience.