Adaptive mHC for Edge Devices: Joint Manifold Constraint and Hardware-aware Architecture Search

TL;DR: Let’s make mHC not just smart, but efficient for tiny devices! What if we combine manifold-constrained hyper-connections with hardware-aware neural architecture search to find the best trade-offs for speed and energy use? An initial study could benchmark such models on resource-limited AI chips using image and sensor data.

Research Question: Can joint optimization of manifold constraints and network architectures tailored for specific hardware significantly improve the deployment efficiency of mHC models on edge devices?

Hypothesis: Co-designing mHC’s manifold constraints with hardware-aware architecture search will yield models that maintain accuracy while drastically reducing energy and memory requirements on edge accelerators.

Experiment Plan: - Setup: Integrate a hardware-aware NAS framework (e.g., as in Zniber et al., 2025) with mHC, allowing both the network’s architecture and the manifold constraint to be optimized for a given hardware profile.

• Data: CIFAR-10 (vision), PTB XL (ECG), or IoT sensor datasets.
• Measurements: Model accuracy, energy consumption per inference, memory usage, latency on real edge hardware (e.g., ARM Cortex, NVIDIA Jetson).
• Expected Outcome: The optimized mHC models should approach or surpass baseline accuracy while using significantly less energy and memory.

References:

• Xie, Z., et al. (2025). mHC: Manifold-Constrained Hyper-Connections.
• Zniber, A., Symons, A., Karrakchou, O., Verhelst, M., & Ghogho, M. (2025). Hardware-aware Neural Architecture Search of Early Exiting Networks on Edge Accelerators.
• Wöhrle, H., Schneider, F., Schlenke, F., De Lucas Alvarez, M., Kirchner, F., & Karagounis, M. (2023). Multi-Objective Surrogate-Model-Based Neural Architecture and Physical Design Co-Optimization of Energy Efficient Neural Network Hardware Accelerators. IEEE Transactions on Circuits and Systems Part 1: Regular Papers.