Dynamic Pipeline Morphing for Energy-Proportional RISC-V

Kumar & Bhattacharya (2025) optimized a static 5-stage RISC-V pipeline, but pipelines are typically fixed. This research proposes "morphable" pipelines using clock-gating and stage bypassing, similar to MaRVIn’s configurable ALUs (Armeniakos et al., 2025). For light workloads (e.g., IoT sensors), the core collapses to 3 stages to save power; for HPC tasks, it expands to 5+ stages. A microcontroller analyzes IPC (instructions-per-cycle) metrics to trigger morphing, leveraging insights from SENECA’s efficiency trade-offs (Tang et al., 2023). Unlike Rajyan & Saini’s modular RISC-V (2024), this reconfigures timing rather than just functionality. It addresses the rigidity of conventional pipelines (e.g., Serpa et al.’s MIPS design, 2023) by making energy consumption proportional to computational demand.

References:

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