Hardware-Aware Co-Design of Efficient Time Series Foundation Models

TL;DR: Can we make time series foundation models even more efficient by tailoring their design to specific edge hardware? Let's co-optimize small hybrid models like Reverso and their data pipelines for ARM, FPGA, or neuromorphic chips, and see how much further we can push the performance-efficiency frontier.

Research Question: How much additional efficiency and accuracy can be gained by co-designing small hybrid time series foundation models and their inference/data pipelines for deployment on specific hardware platforms?

Hypothesis: Jointly optimizing model architecture (layer types, memory access patterns, quantization) and hardware-specific pipelines will substantially outperform generic deployments, making real-time zero-shot forecasting feasible on low-power edge devices.

Experiment Plan: Profile Reverso and similar models on several hardware backends (CPU, ARM, FPGA, etc.). Use neural architecture search or manual co-design to tailor model components (e.g., convolution kernel sizes, RNN unrolling, quantization) for each hardware type. Benchmark end-to-end latency, energy usage, and accuracy on real-world forecasting tasks. Analyze the trade-offs and provide design guidelines for practitioners.

References:

• Fu, X., Li, Y., Papaioannou, G., & Kim, Y. (2026). Reverso: Efficient Time Series Foundation Models for Zero-shot Forecasting.
• Ashraf, H., Danish, S., Leivadeas, A., Otoum, Y., & Sattar, Z. (2025). Energy-Aware Code Generation with LLMs: Benchmarking Small vs. Large Language Models for Sustainable AI Programming. 2025 3rd International Conference on Foundation and Large Language Models (FLLM).